Professor Sheldon Tan (PI) received  a three-year grant (CCF-1816361) from National Science for  developing new optimization and runtime management techniques for more reliable and robust nanometer ICs. The project is titled “SHF:Small:  EM-Aware Physical Design and Run-Time Optimization for sub-10nm 2D and 3D Integrated Circuits”. This is a three year project starting August 1st, 2018 with $450K budget and the project will develop advanced EM-aware physical optimization techniques and run-time EM mitigation techniques for traditional 2D and emerging 3D stacked ICs in the nanometer regime.

More information about this new award can be found at https://www.nsf.gov/awardsearch/showAward?AWD_ID=1816361&HistoricalAwards=false

Electromigration (EM) has emerged as a major design constraint and reliability issue for nanometer-scale integrated circuits (ICs) and emerging 3D stacked ICs.  Due to its importance, many advances have been made recently in the EM modeling and fast numerical assessment techniques.  However, those advanced EM models have not been fully exploited by existing EM-aware physical design and optimization methods to reduce and mitigate the overly conservative VLSI design practices. The new EM models can naturally consider wire topology and structure impacts on the EM failures of interconnect wires and recovery effects of EM aging process for the first time. As a result, the new EM models open new opportunities for EM optimization at physical design stages. The new EM optimization techniques will improve the industry’s ability to improve IC reliability amid continued aggressive transistor scaling and increasing power density.  This research will also contribute significantly to the core knowledge and technologies of EM-aware physical design and optimization for nanometer VLSI designs. This grant will also enable Dr. Tan to hire more female and underrepresented minority students to further contribute to the diversity in America’s science and technology workforce.