University of California, Riverside

Department of Electrical and Computer Engineering



The Semiconductor Industry’s Nanoelectronics Research Initiative:


The Semiconductor Industry’s Nanoelectronics Research Initiative:
 

By

Jeff Welser

Director, SRC Nanoelectronics Research Initiative, IBM Almaden Research Center

When: Monday, October 5, 2009
Time: 2:00pm - 3:00pm
Location: ENGR2 138

Abstract:

For over 35 years, the ability to achieve increased performance per dollar in microprocessor chips by scaling the dimensions of the field-effect transistor (FET) in Complimentary Metal Oxide Semiconductor (CMOS) technology has been the driving engine behind the global semiconductor industry. However, in recent generations, exponentially increasing power density due to leakage currents as well as active switching energy of these nanoscale transistors is limiting our ability to reap the historical benefits of continued scaling. We are now forced to trade-off performance and density for reduced power consumption, and hence the fundamental physics of the CMOS transistor operation, rather than fabrication capability, will eventually be the ultimate limit for future scaling.

As the ultimate limits to the scaling of CMOS technology are getting closer, completely new approaches in emerging areas in electronics at the nanoscale need to be explored. Recognizing this critical challenge, the Nanoelectronics Research Initiative (NRI) was chartered in 2005 by a consortium of Semiconductor Industry Association (SIA) member companies to develop and administer a university-based program to address this issue.

NRI Mission: Demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 2020 timeframe.

In this talk, the scaling challenges facing current CMOS technology will be discussed, along with the ultimate limits for charge-switching based devices. From this motivation, the current status of the NRI program will be discussed, with an overview of the current research topics being investigated at the NRI centers.

About the Speaker:

Jeff Welser received his PhD in Electrical Engineering from Stanford University in 1995, and joined IBM's Research Division at the T.J. Watson Research Center. His graduate work was focused on utilizing strained-Si and SiGe materials for FET devices. Since joining IBM, Jeff has worked on a variety of novel devices, including nano-crystal and quantum-dot memories, vertical-FET DRAM, and Si-based optical detectors. He has held a variety of management positions in IBM research, as well as IBM's SOI technology development organizations, and is currently on assignment to the Semiconductor Research Corporation (SRC). He is Director of the Nanoelectronics Research Initiative (NRI), managing university-based research on future nanoscale logic devices, and is based at the IBM Almaden Research Center in San Jose, CA. 

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