University of California, Riverside

Department of Electrical and Computer Engineering



Designing Low-power and robust computing systems in nanoscale technology


Designing Low-power and robust computing systems in nanoscale technology
 
Nam Sung Kim
Intel Corporation

Date: Friday, March 2, 2007
Time: 11:00am
Location: A265 Bourns Hall

With ever increasing clock frequency and the number of integrated transistors in a single die, low power consumption becomes a critical concern in the design of computing systems. Furthermore, technology scaling increases the impact of process, temperature, and voltage (PVT) variations and device aging on delay, power, and area of computing systems, resulting in more design margin and diminishing return on technology scaling. The first part of the talk presents exploring the effectiveness of the simultaneous application of pipelining and parallel processing as a total power (static plus dynamic) reduction technique. Previous studies have been limited to either pipelining or parallel processing, but both techniques can be used together to reduce supply voltage at a fixed throughput point. According to our analyses, there exist optimal combinations of pipelining depth and parallel processing width to minimize total power consumption. The experiments show that the optimal combinations of both pipelining and parallel processing can reduce the total power by as much as 44% compared to an optimal system using only pipelining or parallel processing alone. We extend our study to show how process parameter variations affect these results. Our analyses reveal that the variations shift the optimal points to shallower pipelining and narrower parallel processing at a fixed yield point.

The second part of the talk presents circuit and microarchitecture techniques making computing system more robust against PVT variations or device aging. For PVT robustness, supply voltage is tuned by in-situ timing error detection mechanism, eliminating the need for voltage margins. In the event of a timing error, a modified pipeline recovery mechanism restores correct program state. Analyses of a full-custom multiplier and a SPICE-level Kogge-Stone adder model reveal that substantial energy savings are also possible for these devices (up to 64.2%) with little impact on performance due to error recovery (less than 3%). To address on-chip cache device aging problems more accurately, several interesting circuit and microarchitectural experimental results are shown along with two techniques improving on-chip cache failure rate by 5 times.

About the speaker:

Nam Sung Kim received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Taejon Korea, and the Ph.D. degree in computer science and engineering from the University of Michigan, Ann Arbor, in 2004. Currently, he is with the Microprocessor Technology Laboratory in Intel Corporation. He has been publishing more than 25 IEEE/ACM journal and conference papers and serving several conference TPC members. He is also an adjunct instruction at Oregon Graduate Institute teaching an advanced VLSI system design course. He was a recipient of the Design Automation Conference (DAC) Student Design Contest award in 2001, the IEEE MICRO best paper award in 2003 for his work on the low-power and robust microarchitecture, and Intel Fellowship in 2002. His work has focused on computer architecture, digital circuit, and computer aided design, with particular emphasis on robust and low-power computer system design.
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