University of California, Riverside

Department of Electrical and Computer Engineering



Bridging VLSI Design and Manufacturing


Bridging VLSI Design and Manufacturing
 
Puneet Gupta
Blaze DFM Inc.

Date: Friday, February 23, 2007
Time: 11:00am
Location: Bourns A265

The semiconductor industry is at an interesting - and scary - juncture. Design and manufacturing NRE (nonrecurring engineering) costs for a state-of-the-art chip can reach several tens of millions of dollars; this makes the transition to newer processes economically infeasible for low- to medium-volume IC products. Scaling of physical dimensions faster than the optical wavelengths or equipment tolerances used in the manufacturing line has led to increased process variability. This in turn has led to unpredictable design, unpredictable manufacturing, and low yields. As a result of the above trends, future power, performance and cost improvements cannot come from the manufacturing process alone; they depend significantly on design automation technology. Such "equivalent scaling" improvements - perhaps as much as one full technology generation - must come from new synergies between various "silos"  of the design to manufacturing flow.

Today, design for manufacturing ("DFM") is the new buzzword in design automation, manufacturing automation, semiconductor and semiconductor equipment industries alike. My work in this still-nascent research area has developed new bidirectional data flows and techniques that bridge design and manufacturing, and that address the challenges of (1) high cost of design, (2) high cost of manufacturing, (3) low manufacturing yield, and (4) disconnects between design and the manufacturing process. In this talk, I will first briefly sketch the design and manufacturing flows, then show how the challenges of low predictability and high variability in modern integrated circuits can be addressed by new design techniques that are explicitly aware of manufacturing limitations. I will give examples of how leakage power variability and timing variability can be mitigated by such manufacturing-aware design methods. I will also give examples of new design-aware manufacturing flows that better capture the designer's intent in silicon. The talk will conclude with several directions for future research.

About the speaker:

Puneet Gupta received the B.Tech degree in Electrical Engineering from Indian Institute of Technology, Delhi in 2000. He joined the Electrical and Computer Engineering department at  University of California, San Diego in 2001 where he is currently a Ph.D. candidate. He has been at Blaze DFM Inc. since 2004 as co-founder and product architect. Puneet's research has focused on building high-value bridges between physical design and semiconductor manufacturing for lowered cost, increased yield and improved predictability of integrated circuits. He has authored over 40 papers and is a recipient of  IBM Ph.D. fellowship. He holds one US patent and has 12 pending. He has given tutorial talks at ICCAD, WesCon, CMP-MIC, UC Santa Cruz and UC San Diego and is a short-course instructor at SPIE Advanced Lithography, 2007. 



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Electrical and Computer Engineering
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