University of California, Riverside

Department of Electrical and Computer Engineering

ESD+RF IC Co-Design Methodology

ESD+RF IC Co-Design Methodology
Albert Wang
Department of Electrical and Computer Engineering, Illinois Institute of Technology

Date: Friday, February 16, 2007
Time: 11:00am
Location: Bourns A265

On-chip electrostatic discharge (ESD) protection circuitry design emerges as a grand challenge to RF IC designs recently. While typically RF ICs demand for more robust ESD protection solutions, RF circuit is extremely sensitive to any parasitic effects associated with ESD protection structures, which inevitably affect circuit performance of RF IC cores under protection. For example, ESD-induced parasitics will corrupt the critical I/O Z-matching of RF ICs. Hence, the complex interactions between the ESD protection circuitry and the RF IC cores must be fully addressed in practical RF IC designs. This talk presents a new ESD+RF co-design methodology that allows whole-chip design optimization for both RF ICs and ESD protection circuitry. Practical ESD-aware RF IC design examples will be discussed.

About the speaker:

Albert Wang received a BSEE degree from the Tsinghua University, China, in 1985, a MSEE degree from the Chinese Academy of Sciences in 1988, and a PhD EE degree from The State University of New York at Buffalo in 1995. He has more than six years of industrial experience, most recently with the National Semiconductor Corporation in the Silicon Valley. In 1998, He joined the Department of Electrical and Computer Engineering at the Illinois Institute of Technology (IIT), where he is currently an Associate Professor and Director for the Integrated Electronics Laboratory. His research interests focus on Analog/Mixed-Signal/RF ICs, Advanced on-Chip ESD Protection, IC CAD and Modelling, Systems-on-a-Chip (SoC), and Advanced Semiconductor Devices, etc.

Wang received the CAREER Award from the National Science Foundation in 2002 and the inaugural Sigma Xi Award for Excellence in University Research from IIT in 2003. He authors the book “On-Chip ESD Protection for Integrated Circuits” (Kluwer Academic Press, 2002) and more than 110 peer-reviewed papers in the field, and holds four U.S. patents.
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