University of California, Riverside

Department of Electrical and Computer Engineering

Low Power, High Performance and Nanometer-era Digital CMOS Circuit Design

Low Power, High Performance and Nanometer-era Digital CMOS Circuit Design
Carl Sechen
Professor, University of Washington

Date: February 28, 2005
Time: 11:00 am
Location: Bourns Hall A265

I will overview my research group’s work in the area of low power, high performance and nanometer-era digital CMOS circuit design. For example, we have assembled what appears to be the lowest power design flow for static CMOS circuits. The design flow features single-pass timing closure using a unique variable die routing approach, coupled with an optimal cell library. Digital blocks of the size needed for contemporary mixed signal circuits are easily handled. A key aspect of the design flow is a gate sizer that exhibits optimality, based on a new gate delay model accurate to within 5% of Hspice over an extremely wide range of input slews and load ratios. We are developing Cadence design kits, cell libraries, and complete synthesis and layout flows for well-into-the-future processes, from 45nm, 32nm, … , 8nm, etc. These open-source kits and flows will enable both digital and analog designers at other universities and at companies to determine the correct design methodologies now for future nanometer-era technologies. I will also describe our new low power, self-clocked differential output prediction logic (DOPL) technique. DOPL is twice as fast as domino logic and was used to fabricate by far the fastest 64b adder ever reported. I will also briefly overview work on radiation-hard-by-design SRAMs that mitigate SEUs in the memory cells and SETs in the peripheral circuitry, including not only 6T memory cells but also 1T1C cells. Lastly, I will touch on a complete asynchronous design flow based on locally-clocked dynamic logic (LCDL). LCDL yields the highest throughput micropipelines compared to all previously published approaches, indeed up to a remarkable 4.3 GHz for the IBM 0.13um process.


Carl Sechen received his B.E.E. from the University of Minnesota, an M.S. from M.I.T., and a Ph.D. from UC Berkeley. Starting in 1986, he was an Assistant and then Associate Professor in the Department of Electrical Engineering at Yale University. In 1992 he moved to the University of Washington, where he is now Professor in the Department of Electrical Engineering. He is a co-director of the National Science Foundation’s Center for the Design of Analog and Digital Integrated Circuits (CDADIC). Prof. Sechen was named an IEEE Fellow in 2002. He received the Semiconductor Research Corporation’s “1994 SRC Technical Excellence Award”. He also received the Semiconductor Research Corporation’s “1988 SRC Inventor's Award”. An “SRC Inventor’s Recognition Award” was received in 2001 for his development of output prediction logic. He received the “Outstanding Project Award” from NSF CDADIC in 2002, and Washington’s EE department “Outstanding Research Advisor Award” also in 2002. In his 18 years as a professor, Prof. Sechen has graduated 17 Ph.D. students. He currently advises 13 Ph.D. students in his VLSI Design and CAD Laboratory. He has authored one book, two patents, and authored or coauthored 141 research papers. He is a co-founder of, Inc., a placement and routing tool vendor.
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