University of California, Riverside

Department of Electrical and Computer Engineering



Robust Low-Power Design for Nanometer Technology


Robust Low-Power Design for Nanometer Technology
 
Kevin Cao
Berkeley Wireless Research Center
University of California, Berkeley

Date: April 21, 2004
Time: 11:00 am
Location: Bourns Hall A171

Rapid scaling in technology has posed grand challenges for integrated circuit design in the nanometer regime. The most critical issues are power dissipation and circuit parametric variations; their scaling trends are not promising. In this situation, design strategies need to be changed adaptively to overcome these looming constraints. One of the most promising solutions is ultra-low voltage (Vdd) design, which effectively reduces both switching and standby energy consumption. However, designs operating under ultra-low Vdd face severe reliability problems in both data preservation and logic operation. In this talk, a variety of design methodologies will be presented to achieve both system robustness and power efficiency, covering the designs of on-chip memory, logic circuits, and interconnects. First, a sub-150mV Vdd SRAM design will be presented that realizes both reliable functionality and over 90% leakage reduction. Then, to design robust low-power logic circuits, tradeoffs in timing, power, and variability will be examined during the optimization of supply voltage, threshold voltage, and sizing. In addition, the reliability of on-chip interconnect designs will also be discussed.

Biography:

Kevin Cao is currently a post-doctoral researcher at the Berkeley Wireless Research Center, University of California, at Berkeley. He received his B.S. in physics from Peking University in 1996, and his M.A. in biophysics and Ph.D. in electrical engineering from UC Berkeley in 1999 and 2002, respectively. Dr. Cao's research areas include robust low-power design techniques for nanometer technology; design for manufacturability issues; high-speed interconnect design; hardware/software co-design for digital imaging systems.
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Electrical and Computer Engineering
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